Scaling Compute To Satiate AI

Fifty years ago, DRAM inventor and IEEE Medal of Honor recipient Robert Dennard created what essentially became the semiconductor industry’s path to perpetually increasing transistor density and chip performance. That path became known as Dennard scaling, and it helped codify Gordon Moore’s postulate about device dimensions shrinking by half every 18 to 24 months. For decades it compelled engineers to push the physical limits of semiconductor devices.

But in the mid-2000s, when Dennard scaling began running out of juice, chipmakers had to turn to exotic solutions like extreme ultraviolet (EUV) lithography systems to try to keep Moore’s Law on pace. On a visit to GlobalFoundries in Malta, N.Y., in 2017 to see the company install its first EUV system, senior editor Samuel K. Moore asked one expert what the fab would need to achieve even smaller device dimensions. “We’d probably have to build a particle accelerator under the parking lot,” the man joked. The idea seemed so fantastic that it stuck with Moore.

So when Tokyo-based tech journalist John Boyd recently pitched a story about an effort to harness a linear accelerator as an EUV light source, Moore was excited. Boyd’s visit to the High Energy Accelerator Research Organization, known as KEK, in Tsukuba, Japan, became the basis for “Is the Future of Moore’s Law in a Particle Accelerator?” As he reports, KEK’s system generates light by “boosting electrons to relativistic speeds and then deviating their motion in a particular way.”

So far, KEK researchers have managed to blast a 17-megaelectron-volt electron beam in bursts of 20-micrometer infrared light, a ways away from the current industry standard of 13.5 nanometers. But the KEK team is optimistic about their technology’s prospects.

While the industry’s ability to affordably make smaller devices has certainly slowed, Moore believes that scaling has a few tricks up its sleeve yet. In addition to brighter light sources like the one KEK is working on, future complementary field-effect transistors (CFETs) will build two transistors in the space of one.

“I believe Wong and Liu want young, technically minded people to understand the importance of keeping semiconductor advances going and to make them want to be part of that effort,” Moore says.

In the shorter term, Moore says stacking chips is the most effective way to keep increasing the amount of logic and memory you can throw at a problem.

“There are always going to be functions in a CPU or GPU that don’t scale as well as core processor logic. Increasingly, it doesn’t make sense to try to keep building all these parts using the core logic’s bleeding-edge chip processes,” Moore says. “It makes more sense to build each part with its best, most economical process, and put them back together as a stack, or at least in the same package.”

To meet the demands of the booming AI sector, makers of GPUs will need to stack up. When former Taiwan Semiconductor Manufacturing Co. chairman Mark Liu and TSMC chief scientist H.-S. Philip Wong wanted to get their message out about the future of CMOS, they approached Moore. The result is “The Path to a 1-Trillion-Transistor GPU.” In addition to Wong’s corporate role, he’s also an academic. One of the worries he’s repeatedly expressed to Moore is that AI and software generally are pulling talent away from semiconductor engineering.

“I believe Wong and Liu want young, technically minded people to understand the importance of keeping semiconductor advances going and to make them want to be part of that effort,” Moore says. “They want to show that semiconductor engineering has a career-long future despite much talk of the death of Moore’s Law.”

​IEEE Spectrum